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rev. 0.5 10/13 copyright ? 2013 by silicon laboratories AN650 AN650 si468 x s chematics and l ayout g uide 1. introduction this document provides: ?? general si468x design guidelines, which include schematics, layout, and bom ?? si468x fm/fmhd/t-dmb/dab antenna/ma tching network design guidelines 2. si468x wlcsp schematic and layout 2.1. schematic design and component selection this section shows the minimal schematic and layout opti ons required for optimal performance of si468x in the wlcsp package. population options are provided to miti gate system noise, to use analog audio output, and to operate the si468x with crystal. free datasheet http://www..net/
AN650 2 rev. 0.5 2.1.1. schematic design figure 1. si468x wlcsp schematic design free datasheet http://www..net/
AN650 rev. 0.5 3 2.1.2. component selection the l1, l2 and c13 are external components for matching pur poses. this configuration is set up for achieving the best conducted sensitivity result. it is shown here for de monstrating best possible layouts. but when designing with a specific antenna, the exact matching network and com ponent values are referred to in each individual antenna selection in ?4. antenna and matching network design and layout? . l1 and l2 are front-end matching inductors. inductors l1 and l2 are selected to maximize the voltage gain across the dab/t-dmb band. l1 and l2 should be selected with a q of 15 to 20 in the range of 100 mhz to 200 mhz. place l1 and l2 as close as possible to the si468x. al so, route l1 to ground plane with a short trace and a via. drop an in-pad ground via for a6 to connect the pin to ground plane. c13 is required to optimize voltage on the vhfi pin in t he fm/fmhd band. refer to property ?0x1712? of an649 for information on how to handle the vhfsw. the recommendations regarding c1, c2, c3, c5, c6, c7, c8, c9 and c10 are made to reduce the size of the current loop created by the bypass cap and routing, mi nimize impedance and return all currents to the gnd. c1 and c2 (5.6 pf and 2.2 nf) are required bypass capacitors for va supply pin a8. c3 (0.1uf) is an optional bypass capacitor. place c1, c2 and c3 as close as possible to va. c1 and c2 are chosen to mitigate noise in vco frequency range and vhf range respectively. place a via connecting c1, c2, c3 and va pin to the power rail such that the caps are closer to the si468x va pin than the vi a. route c1, c2 and c3 to the ground plane with a short trace and a via directly. c5 (2.2nf) is a required bypass capacitor for vio supply pin g2. c8 (1uf) is an optional bypass capacitor. c5 and c8 are chosen to mitigate noise in the vhf band. place c5 and c8 as close as possible to vio pin g2 and dbyp pin g1. place a via connecting c5, c8 and vio supply g2 to the power rail such that the caps are closer to the si468x vio pin than the via. route c5 and c8 only to dbyp pin directly with a short (6-mil width) low inductance trace. c6 (2.2nf) is a required bypass capacitor for vmem supply pin f1. c9 (1uf) is an optional bypass capacitor. c6 and c9 are chosen to mitigate noise in vhf band. plac e c6 and c9 as close as possible to vmem pin f1 and dbyp pin g1. place a via connecting c6, c9 and vmem supply pin f1 to the power rail such that the caps are closer to the si468x vmem pin than th e via. route c6 and c9 only to dbyp pin directly with a short (6-mil width) low inductance trace. c7 (2.2nf) is a required bypass capacitor for vcore supply pin e1. c10 (1uf) is an optional bypass capacitor. c7 and c10 are chosen to mitigate noise in the vhf band. place c7 and c10 as close as possible to vcore pin e1 and dbyp pin g1. place a via connecting c7, c10 and vcore pin e1 to the power rail such that the caps are closer to the si468x vcore pin than the via. route c7 and c10 only to dbyp directly with a short (6-mil width) low inductance trace. c4 (1uf) is an optional bypass capacitor for dacref pi n d8 if customer uses analog audio output. place c4 as close as possible to dacref and the gnd pin. customers do not need to populate this capacitor if they are using digital audio output only. c11 and c12 (1 uf and 1 uf) are optional ac coupling ca pacitors for analog audio outputs. the value should be selected to work well with the customer?s choice of audio amp. x1 is an optional crystal required only when using the internal oscillator feat ure. place the crystal x1 as close to xtali (pin c8) and xtalo (pin d9) as possible to minimize current loops. free datasheet http://www..net/
AN650 4 rev. 0.5 2.1.3. layout guide the following placement/layout guides are suggested for 6-layer pcb: ?? pcb layer assignment: ?? layer 1 top side placement and routing for rf and analog traces ?? layer 2 routing for analog traces ?? layer 3 gnd plane ?? layer 4 routing for digital traces ?? layer 5 routing for digital traces ?? layer 6 bottom side placement and routing for digital traces ?? minimum 3-mil trace ?? minimum 3-mil trace spacing ?? 6-mil drill 2-mil plating for in-pad vias (t hrough or buried for 2, 4, 5, 6 layers) ?? 6-mil drill 9-mil plating for normal vias ?? minimum 10-mil component spacing ?? power routed by trace ?? 0201 component size or larger figure 2. si468x wlcsp layout design figure 2 shows critical layout with top side placement, key top side routing, and crystal support. all bypass components are placed around t he silicon as close as possible. a few things to note: ?? l1 and c13 should be placed as close as possible to th e chip and as far from noise sources such as clocks and digital circuits as possible. ?? for the va bypass caps, make sure th e cap with the lowest (5.6 pf) value is placed closest to the chip. ?? there are 11 gnda pins which separate the analog an d digital portions of the chip. the pins need to be stitched to the ground plane with an in-pad via. ?? to prevent disturbance on vco operation, a9, c9, and b8 pins need to be stitch ed to the gnd plane with in-pad via and connected with 3-mil trace as shown in the layout figure. ?? to bring out the digital traces, the following ex ample strategy is described for 6-layer pcb: ?? for pins on outer row (or column) of the grid, use in-pad blind vias to drop down to layer 4 and fanout the traces. ?? for pins on 2nd inner row (or column) of the grid, use in-pad blind vias to drop down to layer 5 and fanout the traces. ?? for pins on 3rd or 4th inner row (or column) of the grid, use in-pad blind vias to drop down to the bottom layer and fanout the traces. free datasheet http://www..net/
AN650 rev. 0.5 5 2.1.3.1. bom table 1. required bom ref designator description note c1 va supply bypass capacitor, 5.6 pf, 10%, z5u/x7r c2 va supply bypass capacitor, 2.2 nf, 10%, z5u/x7r c5, c6, c7 vio supply bypass capacitor, 2.2 nf, 10%, z5u/x7r table 2. optional bom ref designator description note l1 ind, 0402, sm, 100nh this value is required for achieving the best conducted sensitivity result. l2 ind, 0402, sm, 68nh this value is required for achieving the best conducted sensitivity result. c3 va supply bypass capacitor, 0.1 ? f, 1 0 % , z 5 u / x 7 r c4 dacref bypass capacitor, 1 ? f, 10% z5u/x7r c8, c9, c10 supply bypass capacitor, 1 ? f, 10%, z5u/x7r c11, c12 audio ac-coupling capacitor, 1 ? f, 10% z5u/x7r c13 ac coupling cap, sm, 0402, 18pf for antenna matching. see value details in section ?antenna and matching network design and layout.? x1 abracon, abm8-19.200mhz- 10-1-u-t, 19.2 mhz for design temperature ranges from ?10 deg c to 60 deg c. contact sili- con laboratories for recommenda- tions with more flexibility. free datasheet http://www..net/
AN650 6 rev. 0.5 3. si468x qfn sc hematic and layout 3.1. schematic design and component selection this section shows the minimal schematic and layout options reserved for optimal performance of the si468x in the qfn package. population options are provided to mitiga te system noise, to use analog audio output, and to operate the si468x with crystal. 3.1.1. schematic design figure 3. si468x qfn schematic design free datasheet http://www..net/
AN650 rev. 0.5 7 3.1.2. component selection the l1, l2 and c13 are external components for matching pur poses. this configuration is set up for achieving the best conducted sensitivity result. it is shown here for de monstrating best possible layouts. but when designing with a specific antenna, the exact matching network and com ponent values are referred to in each individual antenna selection in ?4. antenna and matching network design and layout? . l1 and l2 are front-end matching inductors. inductors l1 and l2 are selected to maximize the voltage gain across the dab/t-dmb band. l1 and l2 should be selected with a q of 15 to 20 in the range of 100 to 200 mhz. place l1 and l2 as close as possible to the si 468x. also, route l1 to ground plane with a short trace and a via. connect pin9 rfref to and only to ground pad of l1 in layout. c13 is required to optimize voltage on the vhfi pin in the fm /fmhd band. refer to property ?0x1712? of an649 for information on how to enable the vhfsw. the recommendations regarding c1, c2, c3, c5, c6, c7, c8, c9 and c10 are made to reduce the size of the current loop created by the bypass cap and routing, mini mize impedance and return all currents to the ground. c1 and c2 (5.6 pf and 2.2 nf) are required bypass capacitors for va supply pin 12. c3 (0.1 uf) is an optional bypass capacitor. place c1, c2 and c3 as close as possible to va. c1 and c2 are chosen to mitigate noise in vco frequency range and vhf range respectively. place a via connecting c1, c2, c3 and va pin to the power rail such that the caps are closer to the si468x va pin than the vi a. route c1, c2 and c3 only to the abyp pin directly with a short (6-mil width) low inductance trace. c5 (2.2 nf) is a required bypass capacitor for vio supply pin 34. c8 (1 uf) is an optional bypass capacitor. c5 and c8 are chosen to mitigate noise in vhf band. place c5 and c8 as clos e as possible to vio pin 34 and dbyp pin 36. place a via connecting c5, c8 and vio supply to th e power rail such that the caps are closer to the si468x vio pin than the via. route c5 and c8 only to dbyp pin directly wit h a short (6-mil width) low inductance trace. c6 (2.2nf) is a required bypass capacitor for vmem supply pin 35. c9 (1 uf) is an optional bypass capacitor. c6 and c9 are chosen to mitigate noise in vhf band. plac e c6 and c9 as close as possible to vmem pin 35 and dbyp pin 36. place a via connec ting c6, c9 and vmem supply pin to the power rail such that the caps are closer to the si468x vmem pin than the via. route c6 and c9 only to dbyp pin di rectly with a short (6-mil width) low inductance trace. c7 (2.2nf) is a required bypass capacitor for vcore supply pin 37. c10 (1 uf) is an optional bypass capacitor. c7 and c10 are chosen to mitigate noise in vhf band. place c7 and c10 as close as possible to vcore pin 37 and dbyp pin 36. place a via connecting c7, c10 and vcor e pin 37 to the power rail such that the caps are closer to the si468x vcore pin than the via. route c7 and c10 only to dbyp directly with a short (6-mil width) low inductance trace. c4 (1uf) is an optional bypass capacitor for dacref pin 17 if cu stomer uses analog audio output. place c4 as close as possible to dacref pin. customers do not need to populate this capacitor if they are using digital audio output only. c11 and c12 (1uf and 1uf) are optional ac coupling capacitors for analog audio outputs. the value should be selected to work well with the customer?s choice of audio amp. x1 is an optional crystal required only when using the internal oscillator feature. place the crystal x1 as close to xtali (pin 15) and xtalo (pin 16) as possible to minimize current loops. free datasheet http://www..net/
AN650 8 rev. 0.5 3.1.3. layout guide the following placement/layout guidelines are suggested for 4-layer pcb: ?? pcb layer assignment: ?? layer 1 top side placement and routing for rf and analog traces ?? layer 2 ground plane ?? layer 3 routing for digital traces and ground plane ?? layer 4 bottom side placement and routing for digital traces ?? minimum 6-mil trace ?? minimum 6-mil trace spacing ?? 6-mil drill 9-mil plating for normal vias ?? minimum 10-mil component spacing ?? power routed by trace ?? 0402 component size or larger figure 4. si468x qfn layout design figure 4 shows critical layout with top side placement, key top side routing, and crystal support. all bypass components are placed around t he silicon as close as possible. a few things to note: ?? l1 and c13 should be placed as close as possible to th e chip and as far from noise sources such as clocks and digital circuits as possible. ?? for the va bypass caps, make sure th e cap with the lowest (5.6 pf) value is placed the closest to the chip. ?? do not tie any gnd pins back to the gnd padd le. stitch the gnd paddle to gnd using vias. free datasheet http://www..net/
AN650 rev. 0.5 9 3.1.3.1. bom table 3. required bom ref designator description note c1 va supply bypass capacitor, 5.6 pf, 10%, z5u/x7r c2 va supply bypass capacitor, 2.2 nf, 10%, z5u/x7r c5, c6, c7 vio supply bypass capacitor, 2.2 nf, 10%, z5u/x7r table 4. optional bom ref designator description note l1 ind, 0402, sm, 100 nh this value is required for achieving the best conducted sensit ivity result. l2 ind, 0402, sm, 68 nh this value is required for achieving the best conducted sensit ivity result. c3 va supply bypass capacitor, 0.1 ? f, 1 0 % , z 5 u / x 7 r c4 dacref bypass capacitor, 1 ? f, 1 0 % z 5 u / x 7 r c8, c9, c10 supply bypass capacitor, 1 ? f, 10%, z5u/x7r c11, c12 audio ac-coupling capacitor, 1 ? f, 1 0 % z 5 u / x 7 r c13 ac coupling cap, sm, 0402, 18 pf this value is required for achieving the best conducted sensit ivity result. x1 abracon, abm8-19.200mhz- 10-1-u-t, 19.2 mhz for design temperature ranges from ?10 to 60 c. contact silicon laboratories for recommendations with more flexibility. free datasheet http://www..net/
AN650 10 rev. 0.5 4. antenna and matching network design and layout 4.1. hp antenna (si468x) the si468x digital radio receiver component supports a headphone antenna interface through the vhfi pin. a headphone antenna with a length of 1.1 m suits fm/fmhd/t-dmb/dab applications well. 4.1.1. headphone antenna design a typical headphone cable will contain th ree or more conductors. the left and right audio channels are driven by a headphone amplifier onto left and right audio conductors and the common audio conductor is used for the audio return path and rf antenna. additional conductors may be used for microphone audio, switching, or other functions, and in some applications the rf antenna will be a sepa rate conductor within th e cable. a representation of a typical application is shown in figure 5. figure 5. a typical hp antenna application free datasheet http://www..net/
AN650 rev. 0.5 11 4.1.2. headphone antenna schematic figure 6. headphone antenna design the headphone antenna implementation requires components l1, l2, c13, f1, f2, and f3 for a minimal implementation. in figure 6, a headphone and circuit with headphone audio common grounded is used. the esd protection diodes and headp hone amplifier components are system components that will be required for proper implementation of any tuner. inductors 1 and 2 are selected to maximize the voltage gain across the dab/t-dmb band. c13 is switched in with vfhsw to ensure the fm/f mhd band is properly resonated. the user should refer to property ?0x1712? of an649 to understand how to enable and disable the switch. ferrite beads f1 and f2 provide a low-impedance a udio path and high-impedance rf path between the headphone amplifier and the headphone. ferrite beads shou ld be placed on each antenna conductor connected to nodes other than the vhfi such as left and right audio, microphone audio, switching, etc. in the example shown in the figure above, these nodes are the left and ri ght audio conductors. ferrite beads should be 2.5 k ? or greater at 100 mhz, such as the murata blm18bd252sn1. high imp edance is desirable to reduce antenna coupling to the other conductors. l1 and l2 are used as audio ground. diodes should be chosen with no more than 1 pf parasitic capacitance, and diode capacitance should be minimized. if d1 and d2 mu st be chosen with a capacitance greater than 1 pf, they should be placed between the ferrite beads and the head phone amplifier to minimize pcb parasitic capacitance. this placement will, however, reduce the effectiveness of the esd prot ection devices. diode d3 may not be relocated and must therefore have a ca pacitance less than 1 pf. note that each diode package contains two devices to protect against positive and negative polarity esd events. figure 7. optional rf shunt capacitors to reduce noise coupling to antenna f2 j1 r t s hp_jack f1 c13 l2 l1 d1 d2 d3 vhfi vhfsw left channel right channel free datasheet http://www..net/
AN650 12 rev. 0.5 as shown in figure 7, optional rf shunt capacitors c2 and c3 may be placed on the left and right audio traces at the headphone amplifier output to reduce the level of di gital noise passed to the antenna. the recommended value is 100 pf or greater, however, the designer should confirm that the headphone amplifier is capable of driving the selected shunt capacitance. table 5. headphone antenna bom ref designator description note l1 ind, sm, 100 nh, murata l2 ind, sm, 36 nh, murata c13 ac coupling cap, sm, 18 pf, murata f1, f2, f3 ferrite bead, sm, 0603, 2.5 k ? , murata, blm18bd252snid d1, d2, d3 ic, sm, esd diode, sot23-3, california micro devices, cm1213 table 6. headphone antenna optional bom ref designator description note c2 sm, 0402, x7r, 100 pf optional rf shunt capacitor c3 sm, 0402, x7r, 100 pf optional rf shunt capacitor free datasheet http://www..net/
AN650 rev. 0.5 13 4.1.3. headphone antenna layout to minimize inductive and capactive coupling, inductors c1 3, l1 and l2 should be placed together close to the si468x and as far from noise sources such as clocks and digital circuits as possible. to minimize shunt capacitance on antenna trace, place ferrite beads f1 and f2 as close as possible to the headphone connector. to maximize es d protection diode effectiveness, pl ace diodes d1, d2, and d3 as close as possible to the headphone connector. if capacitance larger than 1 pf is required for d1 and d2, both components should be placed between f1, f2, and f3 and the headp hone amplifier to minimize antenna shunt capacitance. place the chip as close as possible to the headphone co nnector to minimize antenna trace capacitance. keep the trace length short and narrow and as far above the reference plane as possible, restrict the trace to a microstrip topology (trace routes on the top or bottom pcb layers only), minimize trac e vias, and relieve ground fill on the trace layer. note that minimizing capacitance has the effe ct of maximizing characteristic impedance. it is not necessary to design for 50 ? transmission lines. 4.2. cable antenna (si468x) the charger cable of a consumer product can be used as an fm/fmhd/t-dmb/da b antenna. this section describes how to interface the si46 8x vhfi input to a cable antenna. 4.2.1. cable antenna design a typical cable antenna contains multiple inner wires/ conductors, which are covered with a protective ground shield. the coupling between the wires and the shield can cause the antenna to have large capacitance in the several hundred pf range. in order to boost the re ceived fm/fmhd/t-dmb/dab voltage, it is necessary to minimize this capacitance. this reduction can be achiev ed by placing ferrite beads in series with each of the antenna?s conductors. 4.2.2. cable antenna schematic figure 8. a typical cable antenna application to resonate the cable antenna within the fm band, the an tenna?s capacitance needs to be reduced. as described in section 4.2.1, this reduction can be achieved by placing the ferrite beads in series with each of the antenna?s conductors. the capacitance should be further controlled by limiting the trace length from the cable ground shield and the rf input pin (vhfi input) on the si468x digital radio chip. each of the components in the schematic above is explained in detail below: l1 (120 nh) is the tuning inductor. this is the typical valu e used to resonate the cable antenna in the center of the dab band. l2 (36 nh) is the tuning inductor. this is the typical va lue used to parallel with l1 to resonate the cable antenna in the center of the dab band. c13 (100 pf) is a dc blocking cap placed between the vhfi pin and the cable antenna ground. the capacitor is used to isolate the cable return currents from the l1 (120 nh ) is the tuning inductor. this is the typical value used to resonate the cable antenna in the center of the fm band. f1(1.5 k ? at 100 mhz) is a shunt ferrite to ground at the c able antenna side. a substantial amount of ground return current may flow through the cable antenna shield/groun d because there are multiple conductors inside the cable along with power supply conductors. th e ferrite will divert the gr ound return curr ent of the cabl e antenna to go free datasheet http://www..net/
AN650 14 rev. 0.5 through the shunt ferrite rather than going through the tuning inductor and/or si468x chip. f2 (1.5 k ? at 100 mhz) is a series ferrite placed on the signal conductor in the cable antenna. note that series ferrites should be placed on each signal conductor in the ca ble. the ferrite is used to isolate the signal conductors from the shield/ground. the choice of the ferrite is depen dent upon the type of signal on each individual conductor. if the conductor is used to carry power, then a ferrite with a large dc current carrying capa bility should be used. likewise, if the conductor is used to carry high frequency analog signals, make sure that the ferrite does not filter the high frequency. 4.2.3. cable antenna layout place the chip as close to the cable antenna as possible. this will minimize the trace length going to the cable antenna which will minimize the parasitic capacitance. place the shunt ferrite for the grou nd return current as close to the cable as possible. putting the shun t ferrite for the ground return current close to the cable ensures that the ground return current ha s minimal loop which will reduce noise coupling. the series ferr ites should be put as close as possible to the cable. this will minimize the parasitic capacitance seen by the vhfi pin. table 7. cable antenna bom ref designator description note l1 ind, sm, 120 nh, murata l2 ind, sm, 36 nh, murata c13 ac coupling cap, sm, 0402, x7r, 100 pf f1 shunt ferrite bead, sm, 0603, 470 ? , 1 a, murata, blm18pg471sn1j rated dc current> max expected ground return current. f2 series ferrite bead, various types. recommended ferrite for power lines: ferritebead, sm, 0603, 470 ? , 1 a, murata, blm18pg471sn1j recommended ferrite for signals: ferritebead, sm, 0603, 2.5k ? , 50ma murata, blm18bd252dn1d for power signals, make sure the rated dc current> max expected ground return current. for all other signals, make sure ferrite does not block/filter the high frequency component of the signals. free datasheet http://www..net/
AN650 15 rev. 0.5 a ppendix a?p rocedure to o ptimize c onducted s ensitivity t hrough v aractor t uning the recommended front-end circuit value is proposed as below: figure 9. recommended front-end network there are 3 properties related with varactor-tuning procedure in each image: the following procedure is intended to show how to achieve the best conducted sensitivit y result for si468x in both fm/fmhd and dmb/dab bands by tuning the on-chip varact or. the end goal is for the customer to identify the desired values of the above 3 properties in each functional fw image. after the part is booted, the 3 properties are set to 0 by default. for each pcb design, the customer needs to set identified values so that the customer can use the automatic tuning function to achieve the ta rget of conducted sens itivity specification. in the tuning command of each image (dab_tune_fre q & fm_tune_freq), there is an antcap parameter. once the antcap is issued with the tuning command as any value other than 0, the automatic tuning function (determined by varm/varb settings) is bypassed and the on-chip varactor is set as the antcap value as specified by users. this feature is ut ilized in the procedure description below. fm/fmhd ?? set fm_tune_fe_cfg property as 1, which closes the vhfsw. ?? how to identify the varactor value for each individual frequency x: 1. connect the signal-generat or to dut with an sma barrel. 2. set the signal-generator to frequency x with 60 db v reading or reaching the max tunable varactor range of 128, whichever events come first. 3. tune si468x to frequency x with antcap set to 1. table 8. varactor tuning properties id fmhd dmb note* 0x1710 fm_tune_fe_varm dab_tune_fe_varm slope of varactor vs frequency curve 0x1711 fm_tune_fe_varb dab_tune_fe_varb inte rcept of varactor vs frequency curve 0x1712 fm_tune_fe_cfg dab_tune_fe_cfg configure vhfsw switch from pin to ground *note: see an649 for detailed descriptions of these properties. ? free datasheet http://www..net/
AN650 16 rev. 0.5 4. call test_get_rssi command 5 times and ge t the average of the 5 rssi measurements. 5. increment the antcap by 1 and re-issue the tune command to si468x. 6. repeat step 4 and step 5 until reach the targeted 60 dbuv reading or reach the max tunable varactor range of 128, whichever events come first. 7. log this value. ?? conduct the test above for frequencies: 88 mhz, 98 mhz, and 108 mhz (and 76 mhz if necessary). ?? if describing the varactor?s relationship with frequency by varactor_value = m/1000 x frequency (in mhz) +b 1. use linear-fit algorithm to calculate m and b. 2. user may want to run more points to get a more accurage equation. ?? when tuning, issue the ?fm_tune_freq $arg 1$freq0? to enable automatic tuning method. dab/dmb ?? set dab_tune_fe_cfg property as 0, which opens the vhfsw. ?? how to optimize varactor value for each individual frequency x: 1. connect the signal-generator to dut with an sma barrel. 2. set the signal-generator to frequency x with 40 dbuv rf level and dab modulation. 3. tune si468x to frequency x with antcap set to 1. 4. call test_get_rssi command 5 times and get the average of the 5 rssi measurements. 5. increment the antcap by 1 and re-issue the tune command to si468x. 6. repeat step 4 and step 5 until reaching the max tunable varactor range of 128. 7. identify the varactor va lue with the max rssi reading. ?? repeat the test for frequencies across the dab band. ?? if describing the varactor?s relation ship with frequency by varactor_value=m/1000*frequency (in mhz) +b, m represents the slope (dab_tune_fe_varm), b represents the intercept (dab_tune_fe_varb). given the data collected, identify the low frequency ra nge where the optimal varactor is not lower than 4. this is illustrated in the graph* below. figure 10. varactor vs. frequency chart ?? feed this data section in red circle to linear-fit algorithm to identify the slope m and intercept b. program m and b values into the properties: 0x1710, 0x1711 after si468x is booted. ?? when tuning, issue the ?dab_tune_freq0$freq0? to enable automatic tuning method. ? *note: this graph is taken with silicon laborator ies? si468x wlcsp daughtercard, version 2.0 free datasheet http://www..net/
AN650 rev. 0.5 17 a ppendix b?c lassic f ront -e nd figure 11. matching network silicon labs recommend using the cla ssic front-end matching network shown in figure 11 for the dab-p2 and fmhd-p2 release. the classic front-end network requir es no pcb layout change and can be implemented by replacing components and value as follows: in the meantime, for vhfsw configuration (pro perty dab_tune_fe_cfg), refer to the following: the change addressed in this appendix is applicable for qfn and wlcsp packages. original matching network (refer to figure 11) classic front-end network l1(68 nh) c1 (100 pf) c13 (18 pf) l2 (36 nh) l1(100 nh) l1(120 nh) original matching network (refer figure 11) classic front-end network fmhd switch closed switch open dab switch open switch closed free datasheet http://www..net/
AN650 18 rev. 0.5 a ppendix c?a pplication c ircuit for emi m itigation the application circuit recommended in this appendix is for reducing the on-chip vco radiated emissions and achieving the optimum matching. figure 12. qfn application schematic emi mitigation due to a high frequency (2880?3840 mhz) on-chip vco, there is some conductive and magnetic coupling from the vco to the adjacent traces. the vco fundamental spur leve l can be reduced by adding external filtering and using the proper layout. external filtering ?? add filter network comprising of l3 and c15 on th e rf input trace (vhfi) fo r filtering the vco spur (2880?3840 mhz). the capacitance c15 provides a low impedance path to ground, and inductor l3 provides high impedance to the vco spur. the two component network attenuates the vco spur from reaching external antenna port and radiating out. the values of these components are selected to achieve the balance between the sensitivity and the emission levels. ?? add low pass network c20 & l5 and c21 & l4 on the audio lines right and left respectively for attenuating the vco coupling ?? add ferrite bead l7 on the va supply line for providing high impedance to any vco leakage ?? add high self resonant frequency (>3 ghz) capacitors c2, c6, c7 and c8 on the supply lines to decouple the vco leakage currents. 1uf c12 8.2pf c2 x1 1uf c13 u1 47 26 24 27 36 35 34 33 32 31 10 9 42 40 16 17 11 43 41 18 19 25 12 23 29 28 49 48 22 37 38 30 45 44 21 20 39 15 46 2 3 14 13 7 8 1 4 5 6 smode rstb nvssb abyp nc intb nvsclk xtali sclk vcore nvmosi epad dfs ssb va rout lout vhfsw dacref xtalo rfref vhfi mosi miso dout vio vmem dbyp dclk nvmiso rfref rfref rfref gndd gndd gndd gndd nc nc nc nc nc nc nc nc nc nc nc nc 2.2nf c3 0.1uf c4 l2 22nh c21 8.2pf l1 120nh 1000_ohm_ferrite l7 18nh l3 c20 8.2pf 1000_ohm_ferrite l4 rout 1000_ohm_ferrite l5 c6 8.2pf 8.2pf c7 c15 2.7pf 8.2pf c8 c24 1uf 33pf c1 c23 1uf c22 1uf c11 2.2nf c10 2.2nf c9 2.2nf 1uf c5 gnd vcore nvssb nvmiso nvclk nvmosi dout dfs mosi smode rstb intb miso dclk sclk ssb xtal_out xtal_out xin xin vhfsw ant_in vhfi va vio vmem_c lout si46xx option option matching option free datasheet http://www..net/
AN650 rev. 0.5 19 layout guide the following placement/layout guidelines are suggested for 4-layer pcb: ?? pcb layer assignment: ?? layer 1 top side placement and routing for rf and analog traces ?? layer 2 ground plane ?? layer 3 routing for high frequency digital traces and ground plane ?? layer 4 bottom side placement and routing for low frequency digital traces ?? minimum 6-mil trace ?? minimum 6-mil trace spacing ?? 6-mil drill 9-mil plating for normal vias ?? minimum 10-mil component spacing ?? power routed by trace ?? 0402 component size or larger figure 13. si468x qfn layout design ? free datasheet http://www..net/
AN650 20 rev. 0.5 figure 13 shows critical layout with top side placemen t, top side routing, and crystal support. all bypass components are placed around t he silicon as close as possible. a few things to note: ?? the front end network components shall be placed as cl ose as possible to the chip and as far away from noise sources such as clocks and digital circuits. l2 shall be routed to ground plane with a short trace and a via connection. ?? the lowest value capacitor (8.2 pf) shall be placed the closest to the chip. ?? crystal and audio traces shall be short in length and the recommended trace width is 6 mils. ?? to minimize the loop area, all return currents shall be returned to its source as compactly as possible. front-end matching the components (c1, l1 and l2) are used for transformi ng the source impedance to match the input impedance of the si468x front-end. the component values selected fo r the matching network achieves the best conducted sensitivity when used with 50 ? source impedance. the ma tching components will require optimization when used with an actual antenna having different source impedance than 50 ? . for the dab band, the matching component l2 connected to vhfs w switch will require opt imization to maximize the voltage gain on the vhfi pin. refer to property "0 x1712" of an649 for information on how to handle the vhfsw switch. the voltage gain is maximized by forming a high q parallel lc resonant tank circuit. the inductor of the tank circuit is the parallel combination of l1 and l2. and, the tank capacitance includes the antenna capacitance, capacitance of the external front end networ k, pcb parasitic, internal chip parasitic and internal variable capacitance provided by on-chip varactor tuning. with a given antenna source impedance and the parasitics (pcb and chip internal), the resonant peak of the lc tank circuit across the dab band can be maximized by find ing the right combination of l2 and the internal varactor capacitance. refer to appendix a for additional details on using internal varactor tuni ng. note that the procedure outlined in appendix a for internal varactor tuning is considering the signal generator source impedance (50 ? ) but the same procedure can be used with different antenna source impedance. to measure and optimize the network for a given source impedance, it is recommended to create an antenna model or dummy circuit. the input impedance of the dummy circuit across the dab band should be 50 ? and the output impedance of the dummy circuit should match the antenna source impedance. the in ternal varactor tuning procedure can then be followed after inserting a calibrated dummy circuit between the signal generator and the external front-end matching network. for the fm/fmhd band, the components c1 and l1 will require opti mization. a similar appr oach to dab of using dummy circuit can be followed to find the right combinati on of c1 and l1 for achieving best fm/fmhd sensitivity for a given antenna source impedance. the capacitance provided by the internal varactor is not required for the fm/fmhd band, and therefore, for the fm /fmhd radiated sensitivity optimization it is not required to follow the internal varactor tuning. free datasheet http://www..net/
AN650 rev. 0.5 21 note: the application schematic and the layout shown in this appendix are applicable for wlcsp package as well. refer to the main layout guide for wlcsp package layout guidance. table 9. application schematic bom ref designator description value manufacture part # c1 cap,sm,0402 33 pf c0402c0g500-330jnp l3 ind,sm,0402 18 nh lqg15hs18nj02d c15 cap,sm,0402 2.7 pf gjm1555c1h2r7bb01d l1 ind,sm,0402 120 nh lqw15anr12j00d l2 ind,sm,0402 22 nh lqw15an22nh00d c2,c6,c7,c8,c20 and c21 cap,sm,0402 8.2 pf grm1555c1h8r2da01d l4,l5 and l7 ferrite, 0402 1000 ohm blm15hg102sn1d c3,c9,c10 and c11 cap,sm,0402 2.2 nf c0402x7r500-222knp c4,c22,c23 and c24 cap,sm,0402 0.1 f c0402x7r100-104knp c12,c13 and c5 cap,sm,0402 1 f c1005x5r1c105k050bc x1 crystal 19.2 abracon, abm8-19.200mhz- 10-1-u_t, 19.2 mhz free datasheet http://www..net/
AN650 22 rev. 0.5 d ocument c hange l ist revision 0.1 to revision 0.2 ? added qfn section schematic design and layout guide. ? added description of c3 in option bom of wlcsp on page 8. ? changed description of c8, c9, c10 in optional bom of wlcsp on page 8. revision 0.2 to revision 0.3 ? updated schematics (both wlcsp and qfn) to reflect the front-end network recommendation to achieve the best conducted sensitivity. ? updated schematics (both wlcsp and qfn) to reflect a10 production pin-out definition. ? updated wlcsp layout on gnda for dfm optimization. original recommendation in 0.2 has no rf performance difference compared to the current recommendation. ? updated design recommendation for headphone antenna. revision 0.3 to revision 0.4 ? added appendix b?applies to fw release si46xx_130215. ? added appendix c?applies to fw release si46xx_130524. revision 0.4 to revision 0.5 ? changed ?si46xx? to ?si468x? throughout. free datasheet http://www..net/
AN650 rev. 0.5 23 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages. free datasheet http://www..net/

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